The disclosure relates generally to stacked die packages and, more particularly, to cooling mechanisms for stacked die packages.
Recently, three-dimensional integrated circuit (3D IC) packages, or stacked die packages, have provided a possible solution to traditional two-dimensional (2D) ICs in overcoming the interconnect scaling barrier and for improving performance. In stacked die packages, multiple dies are stacked together using vertical through silicon vias (TSVs) where longer wire connections and inter-die input/output (I/O) pads are eliminated. The overall performance is significantly improved with faster and more power efficient inter-core communication across multiple silicon layers.
As effective as 3D IC technology is, 3D IC technology faces critical thermal management challenges. When multiple dies are stacked vertically in a package, the thermal path for dissipating heat generated by the dies is limited. Stacked die packages are typically encapsulated in a material that does not dissipate heat well and, if the heat dissipation problem is not addressed, the dies may overheat during operation leading to possible problems with transistor performance and reliability. To address the heat dissipation problem, cooling systems that use thermal via and liquid micro channels have been proposed. However, such systems are complex and expensive to implement.